10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof
US9997237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Apr 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.