Method for mitigating layout effect in FINFET

US9997360B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Da Yang · San Diego, US
• Yanxiang Liu · San Diego, US
• Jun Yuan · San Diego, US
• Kern Rim · Yorktown Heights, US

Key dates

• Filing date: Sep 21, 2016
• Grant date: Jun 12, 2018
• Expiry date: Sep 21, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.