Semiconductor package including a rewiring layer with an embedded chip
US9997446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.