Dummy features in redistribution layers (RDLS) and methods of forming same
US9997464B2 · kind B2 · utility
57Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.