Dual channel structures with multiple threshold voltages

US9997519B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruqiang Bao · Niskayuna, US
• Michael A. Guillorn · Locke, US
• Vijay Narayanan · New York, US

Key dates

• Filing date: May 3, 2017
• Grant date: Jun 12, 2018
• Expiry date: May 3, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/014
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method of forming a semiconductor structure includes depositing a first work function metal layer in nanosheet channel stacks for first and second CMOS structure each including a first nanosheet channel stack for an nFET and a second nanosheet channel stack for a pFET. The method also includes patterning to remove the first work function metal layer surrounding nanosheet channels in the first nanosheet channel stack of the first CMOS structure and nanosheet channels in the second nanosheet channel stack of the second CMOS structure. The method further includes depositing a second work function metal layer to surround the nanosheet channels in the first nanosheet channel stack of the first CMOS structure and the nanosheet channels in the second nanosheet channel stack of the second CMOS structure. The first CMOS structure has a first threshold voltage and the second CMOS structure has a second threshold voltage.