Static random access memory (SRAM) cells including vertical channel transistors and methods of forming the same
US9997523B2 · kind B2 · utility
1Cited by
15References
4Claims
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Key dates
| Filing date | Jun 23, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Jun 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
Abstract
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.