Semiconductor device including channel structure
US9997538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
Abstract
A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked. Separation patterns are disposed to penetrate the stacked structure. A channel structure is disposed between the separation patterns. The channel structure includes a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and includes vertical portions extending from the horizontal portion in a vertical direction and penetrating the stacked structure. A lower structure is interposed between the horizontal portion and the separation patterns. A dielectric structure is interposed between the vertical portions and the stacked structure and extends between the horizontal portion and the stacked structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.