Logic chip including embedded magnetic tunnel junctions
US9997563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | May 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.