Package programmable decoupling capacitor array
US9998100B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2015 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Aug 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.