Substrate bias generating circuit
USRE35141E · kind E · reissue
1Cited by
0References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1993 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Oct 29, 2013 |
Classification
- Technology area (CPC —)General
Abstract
The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits .[.comprising.]. .Iadd.including .Iaddend.capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.