Circuital arrangement for preventing latchup in transistors with insulated collectors
USRE35486E · kind E · reissue
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Feb 9, 2015 |
Classification
- Technology area (CPC —)General
Abstract
A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith. In order to prevent latch-ups of the parasite SCR which is formed by the structure of the vertical transistor with insulated collector without limiting the voltage which can be applied between the collector and the emitter thereof to values below the intrinsic breakdown ones, the circuital arrangement comprises an auxiliary PNP transistor the emitter whereof is short-circuited with the emitter of the vertical PNP transistor, the base whereof is connected to the base of the vertical PNP transistor and the collector whereof is connected to the N-type well, and operates as a switch which biases the N-type well at a voltage which is close to the voltage of the emitter of the vertical PNP transistor when the latter is saturated, reverse-biasing the collector/N-well junction, and opens when the vertical PNP transistor is off, limiting. the voltage applied to the collector/N-well junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.