DRAM including an address space divided into individual blocks having memory cells activated by row address signals

USRE37930E1 · kind E1 · reissue

Assignee

• Infineon Technologies AG · DE

Inventor

• Johann Rieger · Monsheim, DE

Key dates

• Filing date: Jan 8, 2001
• Grant date: Dec 10, 2002
• Expiry date: Jan 8, 2021

Classification

• Technology area (CPC —): General

Abstract

A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.