Single chip frame buffer and graphics accelerator
USRE37944E1 · kind E1 · reissue
13Cited by
20References
26Claims
0Family size
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Key dates
| Filing date | Nov 5, 1999 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Nov 5, 2019 |
Classification
- Technology area (CPC —)General
Abstract
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.