Bus-to-bus bridge in computer system, with fast burst memory range
USRE37980E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Nov 3, 2020 |
Classification
- Technology area (CPC —)General
Abstract
A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.