Process for producing semiconductor device
USRE40748E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC —)General
Abstract
A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.