Dual port random-access-memory circuitry

USRE41325E1 · kind E1 · reissue

Assignee

• Altera Corporation · US

Inventors

• Haiming Yu · San Jose, US
• Tony Ngai · Campbell, US
• Kok Heng Choe · Bukit Mertajam, MY

Key dates

• Filing date: Jan 30, 2009
• Grant date: May 11, 2010
• Expiry date: Jan 30, 2029

Classification

• Technology area (CPC —): General

Abstract

Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.