Boundary-scan input circuit for a reset pin
USRE41496E1 · kind E1 · reissue
1Cited by
46References
32Claims
0Family size
Inventors
Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Nov 8, 2026 |
Classification
- Technology area (CPC —)General
Abstract
A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.