Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

USRE41958E1 · kind E1 · reissue

Inventors

• Sandhya Dwarkadas · Pittsford, US
• Rajeev Balasubramonian · Sandy, US
• Alper Buyuktosunoglu · White Plains, US
• David Albonesi · Ithaca, US

Key dates

• Filing date: Dec 21, 2006
• Grant date: Nov 23, 2010
• Expiry date: Dec 21, 2026

Classification

• Technology area (CPC —): General

Abstract

A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.