Delay locked loop circuit and method
USRE43947E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | May 11, 2011 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | May 11, 2031 |
Classification
- Technology area (CPC —)General
Abstract
A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.