Method and mechanism for implementing electronic designs having power information specifications background

USRE44479E1 · kind E1 · reissue

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Qi Wang · Malden, US
• Ankur Gupta · Bengaluru, IN
• Pinhong Chen · Saratoga, US
• Christina Chu · San Jose, US
• Manish Pandey · San Jose, US
• Huan-Chih Tsai · Saratoga, US
• Sandeep Bhatia · Savanuru, IN
• Yonghoa Chen · Groton, US
• Steven Sharp · North Berwick, GB
• Vivek Chickermane · Ithaca, US
• Patrick Gallagher · Apalachin, US
• Mitchell Hines · San Jose, US

Key dates

• Filing date: Jun 12, 2012
• Grant date: Sep 3, 2013
• Expiry date: Jun 12, 2032

Classification

• Technology area (CPC —): General

Abstract

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.