Structure for a multiple-gate FET device and a method for its fabrication
USRE45165E1 · kind E1 · reissue
4Cited by
14References
17Claims
0Family size
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Key dates
| Filing date | Feb 14, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Feb 14, 2032 |
Classification
- Technology area (CPC —)General
Abstract
A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.