Processor having execution core sections operating at different clock rates
USRE45487E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC —)General
Abstract
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.