Cache pre-fetch architecture and method

USRE46766E1 · kind E1 · reissue

Assignee

• Marvell Israel (M.I.S.L) Ltd. · IL

Inventors

• Tarek Rohana · Santa Clara, US
• Adi Habusha · Rekhasim, IL
• Gil Stoler · Nofit, IL

Key dates

• Filing date: Jun 30, 2015
• Grant date: Mar 27, 2018
• Expiry date: Jun 30, 2035

Classification

• Technology area (CPC —): General

Abstract

Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.