Strained-channel semiconductor device fabrication
USRE47562E1 · kind E1 · reissue
0Cited by
0References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Oct 27, 2036 |
Classification
- Technology area (CPC —)General
Abstract
A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.