Semiconductor device having a self-forming barrier layer at via bottom
USRE49820E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2019 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Aug 31, 2039 |
Classification
- Technology area (CPC —)General
Abstract
An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.