Inventor · San Jose, CA, US

Ming He

22Patents
6h-index
41Co-inventors
65Inventor score

Filing activity: Mar 16, 2012 → Dec 17, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US8586473B1 Methods for fabricating integrated circuits with ruthenium-lined copper Electricity 36 Active
US8517769B1 Methods of forming copper-based conductive structures on an integrated circuit device Electricity 12 Active
US9431294B2 Methods of producing integrated circuits with an air gap Electricity 10 Active
US9318437B1 Moisture scavenging layer for thinner barrier application in beol integration Electricity 8 Active
US8907483B2 Semiconductor device having a self-forming barrier layer at via bottom Electricity 7 Active
US8753975B1 Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device Electricity 6 Active
US10199270B2 Multi-directional self-aligned multiple patterning Electricity 5 Active
US9087881B2 Electroless fill of trench in semiconductor structure Electricity 4 Active
US8932934B2 Methods of self-forming barrier integration with pore stuffed ULK material Electricity 4 Active
US9691971B2 Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the same Electricity 4 Active
US8673766B2 Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition Electricity 2 Active
US10510675B2 Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light Electricity 1 Active
US9054052B2 Methods for integration of pore stuffing material Electricity 1 Active
US12356665B2 Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods Electricity 0 Active
US11705363B2 Fully aligned via integration with selective catalyzed vapor phase grown materials Electricity 0 Active
US9165770B2 Methods for fabricating integrated circuits using improved masks Electricity 0 Active
US8859419B2 Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device Electricity 0 Active
US9576852B2 Integrated circuits with self aligned contacts and methods of manufacturing the same Electricity 0 Active
US9318436B2 Copper based nitride liner passivation layers for conductive copper structures Electricity 0 Active
USRE47630E1 Semiconductor device having a self-forming barrier layer at via bottom General 0 Active
USRE49820E1 Semiconductor device having a self-forming barrier layer at via bottom General 0 Active
US11978668B2 Integrated circuit devices including a via and methods of forming the same Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.