Integrated circuit device including vertical memory device and method of manufacturing the same
USRE50547E1 · kind E1 · reissue
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16References
20Claims
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Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC —)General
Abstract
In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.