Sequoia Design Systems
2Patents
0Active
2Granted
23Portfolio score
Filing activity: Dec 29, 2000 → Oct 17, 2001
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6562638B1 | Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout | Electricity | 35 | Expired |
| US6681376B1 | Integrated scheme for semiconductor device verification | Electricity | 9 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.