Integrated scheme for semiconductor device verification
US6681376B1 · kind B1 · utility
9Cited by
13References
26Claims
0Family size
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Key dates
| Filing date | Oct 17, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Oct 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for determining device yield of a semiconductor device design, comprises determining statistics of at least one device parameter from at least two device layer patterns; and calculating device yield from the statistics. At least one of the device layer patterns is neither a diffusion layer pattern nor a gate poly layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.