Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout
US6562638B1 · kind B1 · utility
35Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Dec 29, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Dec 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layout to device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.