Memory controller with ring bus for interconnecting memory clients to memory devices
US7849256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2006 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Jul 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.