Avinash N. Ananthakrishnan
76Patents
8h-index
106Co-inventors
77Inventor score
Filing activity: Mar 31, 2011 → Sep 26, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8769316B2 | Dynamically allocating a power budget over multiple domains of a processor | Emerging Cross-Sectional Technologies | 18 | Active |
| US8943340B2 | Controlling a turbo mode frequency of a processor | Emerging Cross-Sectional Technologies | 16 | Active |
| US8832478B2 | Enabling a non-core domain to control memory bandwidth in a processor | Emerging Cross-Sectional Technologies | 13 | Active |
| US8539269B2 | Apparatus and method for high current protection | Emerging Cross-Sectional Technologies | 11 | Active |
| US9158693B2 | Dynamically controlling cache size to maximize energy efficiency | Emerging Cross-Sectional Technologies | 10 | Active |
| US8775833B2 | Dynamically allocating a power budget over multiple domains of a processor | Emerging Cross-Sectional Technologies | 9 | Active |
| US8984311B2 | Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing | Emerging Cross-Sectional Technologies | 8 | Active |
| US9074947B2 | Estimating temperature of a processor core in a low power state without thermal sensor information | Emerging Cross-Sectional Technologies | 8 | Active |
| US9026815B2 | Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor | Emerging Cross-Sectional Technologies | 8 | Active |
| US9141166B2 | Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains | Physics | 8 | Active |
| US9594560B2 | Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain | Emerging Cross-Sectional Technologies | 7 | Active |
| US10216246B2 | Multi-level loops for computer processor control | Emerging Cross-Sectional Technologies | 6 | Active |
| US11099628B2 | Throttling of components using priority ordering | Emerging Cross-Sectional Technologies | 6 | Active |
| US10168758B2 | Techniques to enable communication between a processor and voltage regulator | Emerging Cross-Sectional Technologies | 6 | Active |
| US10705588B2 | Enabling a non-core domain to control memory bandwidth in a processor | Emerging Cross-Sectional Technologies | 4 | Active |
| US10379904B2 | Controlling a performance state of a processor using a combination of package and thread hint information | Emerging Cross-Sectional Technologies | 4 | Active |
| US9037840B2 | Mechanism to provide workload and configuration-aware deterministic performance for microprocessors | Emerging Cross-Sectional Technologies | 4 | Active |
| US10545793B2 | Thread scheduling using processing engine information | Physics | 3 | Active |
| US9606595B2 | Microprocessor-assisted auto-calibration of voltage regulators | Physics | 3 | Active |
| US9098261B2 | User level control of power management policies | Physics | 3 | Active |
| US9471490B2 | Dynamically controlling cache size to maximize energy efficiency | Emerging Cross-Sectional Technologies | 3 | Active |
| US10067553B2 | Dynamically controlling cache size to maximize energy efficiency | Emerging Cross-Sectional Technologies | 3 | Active |
| US10372197B2 | User level control of power management policies | Physics | 2 | Active |
| US10503226B2 | Enhanced power management for support of priority system events | Emerging Cross-Sectional Technologies | 2 | Active |
| US10228755B2 | Processor voltage control using running average value | Emerging Cross-Sectional Technologies | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.