Patent · US Active

Thread scheduling using processing engine information

US10545793B2 · kind B2 · utility

3Cited by

3References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Avinash N. Ananthakrishnan · Portland, US
Vijay Dhanraj · Stuttgart, DE
Russell J. Fenger · Beaverton, US
Vivek Garg · San Mateo, US
Eugene Gorbatov · Hillsboro, US
Stephen H. Gunther · Beaverton, US
Monica Gupta · Santa Clara, US
Efraim Rotem · Haifa, IL
Krishnakanth V. Sistla · Beaverton, US
Guy M. Therien · Beaverton, US
Ankush Varma · Portland, US
Eliezer Weissmann · Haifa, IL

Key dates

Filing date	Sep 29, 2017
Grant date	Jan 28, 2020
Priority date	—
Expiry date	Mar 23, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/5094
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.