Bosco Lan
4Patents
4h-index
13Co-inventors
47Inventor score
Filing activity: May 8, 1996 → Oct 10, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6392290B1 | Vertical structure for semiconductor wafer-level chip scale packages | Electricity | 89 | Expired |
| US6897148B2 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Emerging Cross-Sectional Technologies | 86 | Expired |
| US7521360B2 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Emerging Cross-Sectional Technologies | 37 | Active |
| US5904525A | Fabrication of high-density trench DMOS using sidewall spacers | Emerging Cross-Sectional Technologies | 11 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.