Fabrication of high-density trench DMOS using sidewall spacers
US5904525A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | May 8, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.