Vertical structure for semiconductor wafer-level chip scale packages
US6392290B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Apr 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.