Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations
US11263151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Nov 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.