Targeted test fail injection
US11335426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for targeted test fail injection are described. A memory device may include self-test circuitry configured to test one or more memory cells of a memory array. The self-test circuitry may be configured to store one or more addresses to fail during a test of the memory array based on an indication from a mode register of the memory device. The self-test circuitry may be configured to fail the stored one or more addresses regardless of the outcome of the test at the one or more memory addresses. For example, when an accessed address matches a stored address during test, the self-test circuitry may generate an indication that the accessed address has failed one or more tests of the self-test procedure. Based on the self-test circuitry failing the stored addresses, a test of the memory array may be validated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.