Harry J. Wise
10Patents
1h-index
11Co-inventors
43Inventor score
Filing activity: Sep 20, 2016 → Sep 25, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10198849B1 | Preloading translation and data caches using on-chip DMA engine with fast data discard | Physics | 3 | Active |
| US10558489B2 | Suspend and restore processor operations | Physics | 1 | Active |
| US11809558B2 | Hardware security hardening for processor devices | Electricity | 0 | Active |
| US11144329B2 | Processor microcode with embedded jump table | Physics | 0 | Active |
| US11900123B2 | Marker-based processor instruction grouping | Physics | 0 | Active |
| US10180789B2 | Software control of state sets | Physics | 0 | Active |
| US10096081B2 | Adaptive filtering of packets in a graphics processing system | Physics | 0 | Active |
| US11169811B2 | Graphics context bouncing | Physics | 0 | Active |
| US11537319B2 | Content addressable memory with sub-field minimum and maximum clamping | Electricity | 0 | Active |
| US11900499B2 | Iterative indirect command buffers | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.