Content addressable memory with sub-field minimum and maximum clamping
US11537319B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Dec 11, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Dec 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/74591
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.