Harsh Chilwal
5Patents
2h-index
12Co-inventors
44Inventor score
Filing activity: Aug 23, 2005 → Dec 22, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7546566B2 | Method and system for verification of multi-voltage circuit design | Physics | 4 | Active |
| US10769329B1 | Retention model with RTL-compatible default operating mode | Physics | 3 | Active |
| US7558287B2 | Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) | Electricity | 2 | Active |
| US11797742B1 | Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design | Physics | 1 | Active |
| US8255859B2 | Method and system for verification of multi-voltage circuit design | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.