Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design
US11797742B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jan 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.