Inventor · Santa Clara, CA, US

Jeffrey P. Patton

10Patents
4h-index
10Co-inventors
46Inventor score

Filing activity: Jul 7, 2003 → Oct 3, 2006

Most-cited inventions

PatentTitleAreaCited byStatus
US6969678B1 Multi-silicide in integrated circuit technology Electricity 4 Expired
US7064067B1 Reduction of lateral silicide growth in integrated circuit technology Electricity 4 Expired
US8102009B2 Integrated circuit eliminating source/drain junction spiking Electricity 4 Active
US7023059B1 Trenches to reduce lateral silicide growth in integrated circuit technology Electricity 4 Expired
US7843015B2 Multi-silicide system in integrated circuit technology Electricity 3 Active
US7132352B1 Method of eliminating source/drain junction spiking, and device produced thereby Electricity 0 Expired
US7049666B1 Low power pre-silicide process in integrated circuit technology Electricity 0 Expired
US7151020B1 Conversion of transition metal to silicide through back end processing in integrated circuit technology Electricity 0 Expired
US7005376B2 Ultra-uniform silicides in integrated circuit technology Electricity 0 Expired
US7307322B2 Ultra-uniform silicide system in integrated circuit technology Electricity 0 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.