Ultra-uniform silicide system in integrated circuit technology
US7307322B2 · kind B2 · utility
0Cited by
10References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.