Low power pre-silicide process in integrated circuit technology
US7049666B1 · kind B1 · utility
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17Claims
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Key dates
| Filing date | Jun 1, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.