Joseph Doller
3Patents
1h-index
9Co-inventors
33Inventor score
Filing activity: Jun 26, 2015 → Dec 4, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9679658B2 | Method and apparatus for reducing read latency for a block erasable non-volatile memory | Physics | 13 | Active |
| US11462273B2 | SSD with reduced secure erase time and endurance stress | Physics | 1 | Active |
| US12362016B2 | Read latency reduction for partially-programmed block of non-volatile memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.