Read latency reduction for partially-programmed block of non-volatile memory
US12362016B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Dec 4, 2020 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Aug 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.