Method and apparatus for reducing read latency for a block erasable non-volatile memory
US9679658B2 · kind B2 · utility
13Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.