Mark Leinwander
19Patents
8h-index
11Co-inventors
69Inventor score
Filing activity: Nov 28, 1997 → Sep 3, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8495467B1 | Switchable on-die memory error correcting engine | Physics | 35 | Active |
| US5867721A | Selecting an integrated circuit from different integrated circuit array configurations | Physics | 23 | Expired |
| US8898417B1 | Block-based storage device with a memory-mapped interface | Physics | 13 | Active |
| US9123409B2 | Memory device for a hierarchical memory architecture | Emerging Cross-Sectional Technologies | 11 | Active |
| US8793554B2 | Switchable on-die memory error correcting engine | Physics | 10 | Active |
| US8412987B2 | Non-volatile memory to store memory remap information | Physics | 10 | Active |
| US9626327B2 | Memory device for a hierarchical memory architecture | Emerging Cross-Sectional Technologies | 10 | Active |
| US9116800B2 | Block-based storage device with a memory-mapped interface | Physics | 9 | Active |
| US9015440B2 | Autonomous memory subsystem architecture | Physics | 8 | Active |
| US10776200B2 | XOR parity management on a physically addressable solid state drive | Physics | 5 | Active |
| US9779057B2 | Autonomous memory architecture | Physics | 4 | Active |
| US9612750B2 | Autonomous memory subsystem architecture | Physics | 4 | Active |
| US10388330B1 | Using out-of-band signaling to communicate with daisy chained nonvolatile memories | Emerging Cross-Sectional Technologies | 3 | Active |
| US9741398B1 | Using out-of-band signaling to communicate with daisy chained nonvolatile memories | Emerging Cross-Sectional Technologies | 2 | Active |
| US10031879B2 | Memory device for a hierarchical memory architecture | Emerging Cross-Sectional Technologies | 2 | Active |
| US10769097B2 | Autonomous memory architecture | Physics | 1 | Active |
| US9239759B2 | Switchable on-die memory error correcting engine | Physics | 1 | Active |
| US10725956B2 | Memory device for a hierarchical memory architecture | Emerging Cross-Sectional Technologies | 1 | Active |
| US11586577B2 | Autonomous memory architecture | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.