Memory device for a hierarchical memory architecture
US10031879B2 · kind B2 · utility
2Cited by
5References
20Claims
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Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy and/or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. Other embodiments are discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.